1. Field of the Invention
The invention relates generally to the testing of electronic circuits, and more particularly to systems and methods for using logic built-in self-test (LBIST) circuitry to identify the existence of circuit defects that are manifested when the circuit is used at normal operating speeds but not when the circuit is used at slower speeds.
2. Related Art
Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Finally, after the device is manufactured, it may be necessary to test the device at normal operating speeds (“at speed”) to ensure that it continues to operate properly during normal usage.
One way to test for defects in a logic circuit is a deterministic approach. In a deterministic method, each possible input pattern is applied at the inputs of the logic circuit, with each possible set of state values in the circuit. The output pattern generated by each set of inputs and state values is then compared with the expected output pattern to determine whether the logic circuit operated properly. If the number of possible input patterns and number of states is large, however, the cost of deterministic testing of all the combinations is generally too high for this methodology to be practical. An alternative method of testing that has a lower cost is therefore desirable.
One alternative is a non-deterministic approach in which pseudorandom input test patterns are applied to the inputs of the logic circuit. The outputs of the logic circuit are then compared to the outputs generated in response to the same pseudorandom input test patterns by a logic circuit that is known to operate properly. If the outputs are the same, there is a high probability that the logic circuit being tested also operates properly. The more input test patterns that are applied to the logic circuits, and the more random the input test patterns, the greater the probability that the logic circuit under test will operate properly in response to any given input pattern. This non-deterministic testing approach is typically easier and less expensive to implement than a deterministic approach.
One test mechanism that can be used to implement a deterministic testing approach is a built-in self-test (BIST.) This may also be referred to as a logic built-in self-test (LBIST) when applied to logic circuits. BIST and LBIST methodologies are generally considered part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies impact the actual designs of the circuits that are to be tested. LBIST methodologies in particular involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the operation of the circuit's logic gates.
In a typical LBIST system, LBIST circuitry within a device under test includes a plurality of scan chains interposed between levels of the functional logic of the device. Pseudorandom patterns of bits are generated and stored in the scan chains. The pseudorandom bit patterns are then propagated through the functional logic of the device under test and captured in a subsequent scan chain. The data can then be examined to determine whether the results are as expected. For example, the bit patterns produced by a device under test can be compared to he bit patterns produced by a device that is known to operate properly.
This methodology can detect various different types of errors in the device under test, including “at-speed” errors (which occur when the device is operated at a normal operating speed, but not when the device is operated at a slower test speed.) This methodology cannot differentiate between at-speed errors and other types of errors—it can only detect that some type of error occurred. Further, because the bit patterns that are produced by the device during each test loop are combined with the results of many oter test loops, it is impossible to determine the sources of individual errors.
It would therefore be desirable to provide systems and methods for LBIST testing that are capable of detecting errors that only occur at normal operating speeds and that are capable of localizing the sources of these errors.